Experimental Demonstration of Probabilistic Spin Logic by Magnetic Tunnel Junctions

Author / Creator

MMM 2020 (2020)

Conferences

MMM 2020 G4: Neuromorphic Computing with Nanomagnets (2020)

Available as

Online

Summary

The recently proposed probabilistic spin logic (PSL) offers promising solutions to novel computing applications[1], including some that have previously been covered by quantum computing. The PSL's ...

The recently proposed probabilistic spin logic (PSL) offers promising solutions to novel computing applications[1], including some that have previously been covered by quantum computing. The PSL's basic element is probabilistic bit (p-bit). A p-bit outputs random signals continuously while the mean of the output signal is input-dependent. When multiple p-bits are coupled through a network, a PSL is built. So far, several task implementations of PSL, including invertible logic gate, have been simulated numerically. Here, we report an experimental demonstration of a magnetic tunnel junction (MTJ) based hardware implementation of PSL[2]. Differently from the original p-bit proposals, we propose using two biasing methods, magnetic field and voltage, on the MTJ to excite and fine tune the random fluctuation of MTJ[3]. Therefore, our proposed hardware implementation of p-bit carries the benefit of extra tunability of random signal properties, which are eventually used to compensate the variations of mean and rate of random signals due to the intrinsic device-to-device variations of MTJs. As a result, multiple p-bits are tuned to exhibit similar properties even they are built with highly varied MTJs. Another benefit of the proposed p-bit design is that the similar principle could work for not only thermally-unstable MTJs but also thermally-stable MTJs, which are matured for STT-MRAM technologies and are more ready for integration. Then three p-bits are connected by a coupling network so that a PSL of an invertible logic gate is experimentally demonstrated (Fig. 1). As shown in Fig. 2, the invertible AND gate hops between all possible combinations under the AND logic constraint, C=AB. Along with more results from the demonstration, the PSL of an invertible AND logic gate is shown to function as intended. And thanks to the proposed p-bit hardware design that offers high tunability, the entire PSL system does not suffer from the slowest of the system, and shows much greater performance and potential for further scaling.References: [1] K. Y. Camsari, B. M. Sutton, and S. Datta, "P-bits for probabilistic spin logic," Applied Physics Reviews, vol. 6, no. 1. AIP Publishing LLC, p. 011305, 11-Mar-2019. [2] Y. Lv, R. P. Bloom, and J. P. Wang, "Experimental Demonstration of Probabilistic Spin Logic by Magnetic Tunnel Junctions," IEEE Magn. Lett., vol. 10, 2019. [3] B. R. Zink, Y. Lv, and J.-P. Wang, "Independent Control of Antiparallel- and Parallel-State Thermal Stability Factors in Magnetic Tunnel Junctions for Telegraphic Signals With Two Degrees of Tunability," IEEE Trans. Electron Devices, vol. 66, no. 12, pp. 5353-5359, Dec. 2019.

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