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2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) : date, 5-8 Oct. 2015
- Author / Creator
- Available as
- Online
- Summary
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Contributed papers and invited talks on 3 main topics (1) SOI Technology, (2) Subthreshold circuit designs, architectures, and devices, and (3) 3D Integration The combination of these topics makes ...
Contributed papers and invited talks on 3 main topics (1) SOI Technology, (2) Subthreshold circuit designs, architectures, and devices, and (3) 3D Integration The combination of these topics makes this conference the perfect venue to present and learn about the most up to date trends in CMOS and post CMOS Scaling and the low power SOC eco system.
Details
- Creator
- Institute of Electrical and Electronics Engineers
- Format
- Books
- Language
- English
- Publication
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- Piscataway : IEEE, 2015
- Physical Details
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- 1 online resource : illustrations
- ISBNs
- 9781509002597, 1509002596, 150900260X
- New game-changing product applications enabled by SOI,"G. -- Sustaining the silicon revolution: From 3-D transistors to 3-D integration,"T. -- Smart power technologies on SOI,"P. -- ESD protection design with latchup-free immunity in 120V SOI process,"Y. -- Key parameters of BiMOS ESD protection device for UTBB FDSOI advanced technology,"S. -- A âˆ'1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology,"D. -- The missing XDXMOS found! â€" A SOTB circuit acceleration technique using front and back gate interaction,"H. -- Negative capacitance in ferroelectric materials and implications for steep transistors,"A. -- A Î"Vt 0.2V to 1V 0.01mm2 9.7nW voltage reference in 65nm LP/GP CMOS,"G. -- Towards ultra-low-voltage wideband noise-cancelling LNAs in 28nm FDSOI,"G. -- Advantages of subthreshold operation of asymmetric self-cascode SOI transistors aiming at analog circuit applications,"M. -- A 145mV to 1.2V single ended level converter circuit for ultra-low power low voltage ICs,"Y. -- A 10 kgates sub-threshold stream cipher in 180 nm with 6.1 kHz frequency 70 nA total current and 46 nA leakage at 0.33 V,"M. -- Single-well design in FDSOI technology: Towards energy-efficient ultra-wide voltage range digital circuits,"A. -- Essential edge protection techniques for successful multi-wafer stacking,"J. -- Vth self-adjusting tri-gate nanowire MOSFET for stability improvement of SRAM cell operating at 0.1 V,"S. -- Engineered substrates for Moore and more than Moore's law: Device scaling: Entering the substrate era,"C. -- 300 mm InGaAsOI substrate fabrication using the Smart CutTM technology,"S. -- Systematic evaluation of SOI Buried Oxide reliability for partially depleted and fully depleted applications,"W. -- Low voltage devices and circuits for energy-starved systems,"S. -- A 23 nW CMOS ultra-low power temperature sensor operational from 0.2 V,"D. -- Robust subthreshold level conversion,"J. -- Can we connect trillions of IoT sensors in a sustainable way? A technology/circuit perspective (Invited),"D. -- IoT and the cloud: A hacked personality and an empty battery head-ache or an intuitive environment to make our lives easier?,"H. -- Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing,"T. -- Enhanced low voltage digital & analog mixed-signal with 28nm FDSOI technology,"F. -- Technology scaling: The CoolCubeTM paradigm,"F. -- Emerging 3DVLSI: Opportunities and challenges,"Y. -- Logic/memory hybrid 3D sequentially integrated circuit using low thermal budget laser process,"C. -- From nanodevices to nanosystems: The N3XT information technology,"S. -- Monolithic three-dimensional integration for memory scaling and neuromorphic computing,"S. -- Nanowire FET design for 7-nm SOI-CMOS technology,"I. -- On the T-RAM and FED-RAM memory mechanism,"A. -- Asynchronous and synchronous designs for low-power FDSOI CMOS process optimized for subthreshold operation at 0.3V VDD,"C. -- Analog performance improvement of self-cascode structures composed by UTBB transistors using back gate bias,"R. -- CMOS-compatible FDSOI bipolar-enhanced tunneling FET,"P. -- Silicon-on-Ferroelectric-Insulator â€" A comparative analysis of the partially and fully depleted devices,"A. -- Low voltage ripple carry adder with low-granularity dynamic forward back-biasing in 28 nm UTBB FD-SOI,"R. -- Minimum-energy point design in FDSOI Regular-Vt,"L. -- Analysis of deeply scaled multi-gate devices with design centering across multiple voltage regimes,"S. -- Monolithic 3D layout using 2D EDA for embedded memory-rich designs,"I. -- Preliminary steps towards implementing intimate 3D-IC stacking with layer transfer and atomic bonding methods,"M. -- Opportunities and challenges of nanowire-based CMOS technologies,"S. -- Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond,"S. -- Quasi-static analytical model for the dynamic operation of triple-gate junctionless nanowire transistors,"R. -- Transconductance hump in vertical gate-all-around tunnel-FETs,"F. -- Comparative simulation study on MoS2 FET and CMOS transistor,"M. -- A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications,"R. -- Impact of technology and voltage scaling on LEON3 processor performance and energy,"X. -- Subthreshold capable, asynchronous FPGA in a 14nm SOI process,"B. -- A 300nW near-threshold 187.5â€"500 kHz programmable clock generator for ultra low power SoCs,"M. -- Epitaxial layer transfer technology and application,"T. -- Ultrathin chips for flexible electronics and 3D ICs,"J. -- Switch branch in trap-rich RFSOI with 84 dBm off-state IP3,"T. -- Comparative study of parasitic elements on RF FoM in 28 nm FD SOI and bulk technologies,"B. -- SiGe-on-insulator symmetric lateral bipolar transistors,"J. -- Extending the bandwidth of Piezo-Electric energy harvesting through the use of Bias Flip,"S. -- Optimization of gate controlled diode in rectenna for high efficiency RF energy harvesting,"M. -- 0.8-V rail-to-rail operational amplifier with near-Vt gain-boosting stage fabricated in FinFET technology for IoT sensor nodes,"S. -- Modified ELTRAN A game changer for Monolithic 3D,"Z. -- Power, performance, and cost comparisons of monolithic 3D ICs and TSV-based 3D ICs,"D. -- 128 Ã- 96 Pixel-parallel three-dimensional integrated CMOS image sensors with 16-bit A/D converters: By direct bonding with embedded Au electrodes,"M. -- Guidelines on 3DVLSI design regarding the intermediate BEOL process influence,"A. -- Improving performance in near-threshold circuits using 3D IC technology,"S. -- Advanced channel materials for the semiconductor industry,"N. -- Special characterization techniques for advanced FDSOI process,"S. -- Impact of source/drain silicon cap on FDSOI SiGe pMOSFET performance,"E. -- Experimental study on quantum mechanical effect for insensitivity of threshold voltage against temperature variation in strained SOI MOSFETs,"C. -- Full front and back split C-V characterization of CMOS devices from 14nm node FDSOI technology,"B. -- Impact of supercoupling effect on mobility enhancement in UTBB SOI in dynamic threshold mode,"K. -- Low power design: Ramping to production,"C. -- 0.5-V 350-ps 28-nm FD-SOI SRAM array with dynamic power-supply 5T cell,"K. -- A 1kb single-side read 6T sub-threshold SRAM in 180 nm with 530 Hz frequency 3.1 nA total current and 2.4 nA leakage at 0.27 V,"M. -- Design insights for reliable energy efficient OxRAM-based flip-flop in 28nm FD-SOI,"N. -- 10nm Gate-length junctionless gate-all-around (JL-GAA) FETs based 8T SRAM design under process variation using a cross-layer simulation,. --